The present invention relates to devices having thin dielectric barriers. More specifically, the present invention relates to tunnel junctions including, but not limited to, spin dependent tunneling (xe2x80x9cSDTxe2x80x9d) junctions. The invention also relates to information storage devices including, but not limited to, Magnetic Random Access Memory (xe2x80x9cMRAMxe2x80x9d) devices.
A typical MRAM device includes an array of memory cells, word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
In one type of MRAM device, each memory cell includes an SDT junction. The magnetization of an SDT junction assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of xe2x80x980xe2x80x99 and xe2x80x981.xe2x80x99 The magnetization orientation, in turn, affects the resistance of the SDT junction. Resistance of the SDT junction is a first value (R) if the magnetization orientation is parallel and a second value (R+xcex94R) if the magnetization orientation is anti-parallel.
The magnetization orientation of an SDT junction and, therefore, its logic state may be read by sensing its resistance state. However, the memory cells in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other rows and columns. In this regard, the array of memory cells may be characterized as a cross point resistor network.
An SDT junction has an insulating tunnel barrier that is only a few atoms thick. Controlling the fabrication process to produce such thin barriers for an entire array of memory cells is difficult. Some SDT junctions will have a nominal resistance that is significantly lower than the design value. SDT junctions having a significantly low nominal resistance will be referred to as xe2x80x9cdefectivexe2x80x9d SDT junctions.
An SDT junction having a significantly low nominal resistance is unusable in an MRAM device. The defective SDT junction can cause a bit error. In a resistive cross point array that does not use switches or diodes to isolate memory cells from one another, the other SDT junctions in the same column and row as the defective SDT junction will also be rendered unusable. Thus, a single defective SDT junction can cause a column-wide error and a row-wide error.
When data is read back from the MRAM device, error code correction may be used to recover data from a complete column or row of unusable SDT junctions. However, correcting a thousand or more bits in a single column or row is costly, both from a time standpoint and a computational standpoint. Moreover, an MRAM device is likely to have more than one defective SDT junction.
Therefore, a need exists to overcome the problems associated with defective SDT junctions in resistive cell cross point memory arrays.
According to one aspect of the present invention, a defective tunnel junction may be repaired by voltage-exercising the tunnel junction. Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.